Smaller and lighter electronic devices having more advanced functions have been developed. Under such circumstances, it is required that semiconductor devices be more densely packaged. In response to such a requirement, for example, Japanese Unexamined Patent Publications No. 135267/1998 (Tokukaihei 10-135267; published on May 22, 1998) and No. 172157/2004 (Tokukai 2004-172157; Published on Jun. 17, 2004) suggest a method which allows higher density packaging of semiconductor devices by stacking the semiconductor devices.
Incidentally, in stacking of the semiconductor devices having a conventional configuration, a relationship between (i) a height of a connecting terminal of an upper semiconductor device and (ii) a height of sealing resin of a lower semiconductor device is important.
The following describes about this point, with reference to FIG. 15 to FIG. 17. FIG. 15 is a cross sectional view illustrating a stack of two conventional semiconductor devices.
In FIG. 15, a semiconductor device 200 is stacked on a semiconductor device 100. Of the two semiconductor devices, the semiconductor device 100 includes: a base substrate 101; a semiconductor chip 103 mounted on the base substrate 101; external connection terminals 107 provided on a bottom surface of the base substrate 101; and external connection terminals 108 provided on an upper surface of the base substrate 101. The semiconductor chip 103 and the base substrate 101 are electrically connected with each other via a wire 104. Further, the semiconductor chip 103 and the wire 104 are covered with a resin layer 106. On the other hand, a region, of the base substrate 101, where the external connection terminals 108 are provided is not covered by the resin layer 106, and is exposed.
The semiconductor device 200 has the same configuration as that of the semiconductor device 100, except in that a resin layer 106 covers the entire region above a base substrate 101, instead of covering regions other than a region where a semiconductor chip 103 and a wiring 104 are formed.
For example, the following problems may take place in a case where the two semiconductor devices 100 and 200 are stacked as illustrated in FIG. 15. Namely, if a height “s” of each of the external connection terminals 107 of the semiconductor device 200 is lower than a height “t” of the resin layer 106 of the semiconductor device 100, there will be a gap “u” between the external connection terminal 107 of the semiconductor device 200 and one of the external connection terminals 108 of the semiconductor device 100. Due to this gap “u”, it is unable to connect the semiconductor device 100 with the semiconductor device 200. Accordingly, in order to connect the semiconductor device 100 and the semiconductor device 200, it is necessary to satisfy the relationship of “s”>“t”, where “s” is the height of the external connection terminal 107 of the semiconductor device 200, and the “t” is the height of the resin layer 106 of the semiconductor device 100.
If the height “t” of the external connection terminal 107 of the semiconductor device 200 is reduced, the height “t” of the resin layer 106 of the semiconductor device 100 also has to be reduced. However, reduction of the high “t” of the resin layer 106 of the semiconductor device 100 requires a technology for reducing the thickness of the semiconductor device 100: e.g., a technology for reducing the thickness of the semiconductor chip 103, or a technology for lowering the height of the loop formed by the wiring 104. This causes technical difficulty in the production of the semiconductor device 100. A similar problem occurs in a case of stacking semiconductor devices illustrated in FIG. 16.
FIG. 16 is a cross sectional view illustrating a stack of two conventional semiconductor devices. In FIG. 16, a semiconductor device 400 is stacked on the semiconductor device 300. The semiconductor device 300 has an external connection terminal 108 formed on a semiconductor chip 103. A region where the external connection terminal 108 is formed is not covered by a resin layer 106, and the region therefore is exposed. Other than what mentioned above, the configuration of the semiconductor device 300 is the same as that of the foregoing semiconductor device 100. Further, the configuration of the semiconductor device 400 is similar to that of the foregoing semiconductor device 200.
FIG. 17 is a cross sectional view illustrating a resin-sealing process carried out in a manufacturing process of a conventional semiconductor device. In manufacturing of the above mentioned semiconductor device 300, the following problem occurs in the resin-sealing process. Namely, for example, if a transfer mold is used for carrying out the resin-sealing process for covering, with a resin 106, the semiconductor chip 103 except for the region where the external connection terminal 108 is formed, a mold 50 directly presses the wiring layer 108 on the semiconductor chip 103, which layer includes conductive layer x and an insulation layer y (See FIG. 17). The thickness of the wiring layer 108 is approximately 50 μm and is thin. Further, the material of the wiring layer 108 is hardly deformed. As such, the wiring layer 108 will not be able to absorb the stress applied by the mold 50. As a result, a strong stress is applied to the semiconductor chip 103, and this strong stress may cause damage to the semiconductor chip 103.